Micron plans wafer bonding for G11 NAND launch in late 2027
The memory maker targets 42 Gb/mm2 density and 50% faster I/O speeds for its next generation of storage chips.
By Alessia Desai ·
Micron outlined the specifications for its next generation of 3D NAND flash, designated G11, during an event held this week. The company expects to begin ramping production of the new memory in the second half of 2027. The move positions Micron to compete with rivals in high-capacity storage markets.
The new G11 technology will double storage density compared to the current G9 generation. Micron projects the density will rise from approximately 21 Gb/mm2 to 42 Gb/mm2 in triple-level-cell form. This increase exceeds the next-generation NAND offerings currently planned by competitors Kioxia and Samsung.
I/O performance will also improve significantly under the new architecture. Input and output speeds are projected to increase by up to 50%, rising from 3,600 MT/s to 5,400 MT/s. Additionally, the energy required to transfer each bit should decrease by more than 25%.
A key technical shift in G11 involves the adoption of wafer-on-wafer bonding. This method allows Micron to manufacture the NAND array and peripheral circuitry on separate wafers using processes optimized for each specific function. The two wafers are then bonded together, providing more flexibility than the CMOS-under-array designs used in previous generations.
Scott DeBoer, Micron's president and chief technology and products officer, stated that the company had waited for the technology to become cost-effective. "This is the right timing for that technology," DeBoer said. He described G11 as the world's most advanced NAND and confirmed its reliance on wafer-on-wafer bonding.
Micron will also increase the layer count in G11 to over 400. The company has not disclosed the exact number of active wordline layers or memory decks but claims the design will feature an industry-leading memory cell pitch. The density gains are expected to result from a combination of additional layers and smaller cell dimensions.
Beyond G11, Micron plans to continue scaling in all three dimensions. The company is developing new high-mobility materials and ultra-dense cell architectures to improve transistor characteristics and reduce energy consumption. DeBoer noted that the focus remains on densifying cell architecture and continued XYZ scaling, though specific architectural details for future generations have not been disclosed.
